Understanding 0x4000 and 0x4001 RAM

[Cthulhu32]

Hey guys,

I'm going to try to do my own experiments with this, but I want to see what you guys know about this part of the NGPC RAM reading.

=============================================================================
007000 -> 007FFF Sound RAM
=============================

< Z80 ADDRESSES >

0000 -> 0FFF : Shared RAM, mapped to 0x7000 - 0x7FFF in TLCS-900h space

4000 B : Noise Channel & Right Volume.
4001 B : Tone Channel & Left Volume.

8000 B : Z80 <-> TLCS-900h Communication Interface (See TLCS900h - 0x00BC)

C000 B : Write any value to this address to start the Z80 interrupt
in the TLCS-900h code.


So in the above example, what exactly is returned from (4000h) and (4001h)? I'm assuming this is a way for the TLCS900h code to actually read whats going on in the chip, but what kind of data lives here? And Right/Left volume?

[Flavor]

Hey guys,

I'm going to try to do my own experiments with this, but I want to see what you guys know about this part of the NGPC RAM reading.

=============================================================================
007000 -> 007FFF Sound RAM
=============================

< Z80 ADDRESSES >

0000 -> 0FFF : Shared RAM, mapped to 0x7000 - 0x7FFF in TLCS-900h space

4000 B : Noise Channel & Right Volume.
4001 B : Tone Channel & Left Volume.

8000 B : Z80 <-> TLCS-900h Communication Interface (See TLCS900h - 0x00BC)

C000 B : Write any value to this address to start the Z80 interrupt
in the TLCS-900h code.


So in the above example, what exactly is returned from (4000h) and (4001h)? I'm assuming this is a way for the TLCS900h code to actually read whats going on in the chip, but what kind of data lives here? And Right/Left volume?

Man, I don't remember anything about this. Have you looked at the RACE source code to see if it mentions anything useful about it?

[mic_]

A see a couple of possibilities:

1. Reads return whatever you last wrote to 4000/4001
2. Reads return the current left/right output
3. Those registers aren't readable, and return "garbage"

Seems unlikely that any game or demo would read from 4000/4001.

[Cthulhu32]

Yeah I looked at the RACE code, and it returns 0x0 if you request 0x4000 or 0x4001.

I'm stepping through the real BIOS right now, and what I'm seeing is an infinite loop that waits for (0x4000) to be something other than 0.

... disasembly of the real bios ...
00009798: 1D 9D98FF CALL 0FF989Dh ; Call 989D Setup some type of Clock memory function
0000979C: C2 004000 3F 00 CP (004000h),000h ; [0x4000] == 0 (Noise Chip + Left Volume read)
000097A2: 66 F8 JR EQ/Z,000979Ch ; If we are 0x0 (RACE returns this), loop forever.

My next step is putting this in a rom, loading it on my NGPC, and testing various states of write to noise chip, read (4000h), write to tone chip, read (4001h).

[Cthulhu32]

Alright, I have some initial tests! Turns out the Z80 and the tlcs900h read different things from 4000h and 4001h. I've attached the source, binary, and here's a snapshot.

[mic_]

It doesn't look like you ever write to 4000h(?). Might be interesting to try writing a few different values to these locations and print the results. And also to do some writes from the TLCS side.

[Cthulhu32]

Yeah my guess is that the noise setting is coming from the bios, because the bios Z80 driver writes to 4000h during the intro chime. I'm going to implement a couple input buttons that change the noise and tone channels and watch what the values become as my next step.

[Cthulhu32]

So far my results are inconclusive. I'm seeing the TLCS900h read 00 00 for 4000h and 4001h (I had some reading out of order), and now my Z80 is reading 01 0E for 4000h and 4001h. Next step is adding in the Z80 debugger to NeoGPC, then I can figure out what the Z80 driver is writing that allows the TLCS900h read to pick up on. I'm also trying to conceptualize on how to run the two CPUs side by side that does not rely on the tlcs900h.cpp code doing sound executes (driving a cycle forward), but that might be a little too complex for this experiment.